Circuits that include connected logic gates, such as AND, OR, NAND, NOR, XOR and XNOR gates are known as combinational logic circuits. The output values of such circuits depend only on the values of its inputs. Decoders, multiplexers, and adders are common combinational logic circuits used in a variety of applications.
Adders, for example, are useful for many different tasks. Arithmetic/logic units (ALUs) found in most computing devices, include adders. Incrementers are specialized adders which take an n-bit input, n being an integer, and calculate the input plus one. Decrementers, similarly, calculate the input minus one.
A number of distinct arrangements of logic gates exist for producing an incrementer circuit. As with any combinational logic circuit, the design of an incrementer involves a tradeoff between speed and power consumption. An incrementer with a large number of logic gates may require more power to operate than is desirable, in some cases. A seven-stage incrementer runs more slowly than one with only five stages.
Like other combinational logic circuits, some portion of the incrementer circuit may be simplified. The throughput of processing one or more bits of the n-bit logic may be improved in this manner. Ultimately, though, the speed of the incrementer is measured according to the processing speed of the slowest bit. Other phenomena, such as carry propagation and uneven bit loading, such as when the least significant bits (LSBs) are loaded more heavily than the most significant bits (MSBs), can frustrate the efficiency of the incrementer design. Thus, not all simplifications of an incrementer design are worthwhile.
Thus, there is a continuing need to provide an incrementer/decrementer design with an improved throughput.